Method of manufacturing a semiconductor device having trenches for isolation and capacitor

ABSTRACT

At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.

This application is a Continuation application of Application No.10/408,353, filed Apr. 8, 2003, the contents of which are incorporatedherein by reference in their entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a method of manufacture of asemiconductor device, and to the semiconductor device. Moreparticularly, it relates to a method of forming a capacitor inconjunction with a semiconductor device.

In recent years, with the trend toward smaller size, lower powerconsumption, and higher integration of a semiconductor device, theoperating voltage of a semiconductor device has become increasinglylower, and the is voltage supplied from an external power source hasbecome increasingly lower. Under such circumstances, a semiconductordevice is typically equipped with a booster circuit, such as a chargepump circuit, for generating the operating voltage needed by thesemiconductor device from the external power supply voltage. This kindof booster circuit includes a capacitor (capacitive element) which isformed of, for example, a MIS capacitive element utilizing a MISFET(Metal Insulator Semiconductor Field Effect Transistor) as thecapacitor.

Japanese Unexamined Patent Publication No. 2001-85633 (hereinafterreferred to as the first example) discloses the following technology: Ina semiconductor device having a nonvolatile memory, the capacitance of acapacitor of a charge pump circuit is formed such that a firstcapacitance between a first gate and a second gate and a secondcapacitance between the first gate and a well region are connected inparallel to each other. As a result, the area of the charge pump circuitis reduced.

Japanese Unexamined Patent Publication No. Hei 11 (1999)-251547(hereinafter referred to as the second example) discloses the followingtechnology: A first trench capacitor is formed which constitutes thememory cell of a DRAM (Dynamic Random Access Memory), and a secondtrench capacitor, having almost the same configuration as that of thefirst trench capacitor, is formed in another region. The second trenchcapacitor is also used as a capacitor in a region other than that of theDRAM.

Japanese Unexamined Patent Publication No. 2002-222924 (hereinafterreferred to as the third example) discloses a technology forsimultaneously forming a trench for element isolation and a desiredpattern in a region where a capacitive element is formed in asemiconductor substrate.

SUMMARY OF THE INVENTION

In the above-mentioned first example, the boosted voltage value isproportional to the area of the capacitor. For this reason, if the areais reduced with a reduction in size of the device, the areas of a firstgate and a second gate are reduced. As a result, the capacitance isreduced. Therefore, in order to form a high-voltage stable boostercircuit, the area of the capacitors required for a charge pump circuitmust be increased.

In the above-mentioned second example, the number of manufacturing stepsis unfavorably increased, because a capacitor having almost the sameconfiguration as that of the memory cell of the DRAM is formed.

In the above-mentioned third example, a dielectric film and a wiringlayer are formed for forming the capacitive elements. Accordingly, thenumber of manufacturing steps for respectively forming them isundesirably increased.

It is therefore an object of the present invention to provide atechnology which enables an improvement of the capacitor capacitance perunit area.

Further, it is another object of the present invention to provide atechnology for simplifying the manufacturing process in the formation ofa semiconductor device having capacitors.

The foregoing and other objects and novel features of the presentinvention will be apparent from the following description as provided inthis specification and from the accompanying drawings.

Out of the aspects of the present invention disclosed in thisapplication, the general outlines of typical ones will be described asfollows.

Namely, in accordance with the present invention, in a semiconductordevice having semiconductor elements, such as MISFETs, and capacitors(capacitive elements) on a semiconductor device, each of the capacitors(capacitive elements) is formed of a plurality of capacitor formationtrenches formed in a capacitor formation region, a capacitor dielectricfilm formed on the capacitor formation region including the inside ofthe plurality of the capacitor formation trenches, and a capacitorelectrode. As a result, it is possible to increase the surface area ofthe capacitor, and, thereby, to improve the capacitor capacitance perunit area.

Further, in a method of manufacturing a semiconductor device havingsemiconductor elements, such as MISFETs, and capacitors (capacitiveelements) on a semiconductor substrate, at least not less than onecapacitor formation trench is formed by a step of forming an elementisolation trench for isolation between the semiconductor elements in thesemiconductor substrate. As a result, it is possible to increase thesurface area of the capacitor, and, thereby, to improve the capacitorcapacitance per unit area. In addition, it is possible to simplify themanufacturing process. The capacitor formation trench is formed in theshape of a hole or a stripe. Also, by forming it in this manner, it ispossible to increase the surface area of the capacitor, and, thereby, toimprove the capacitor capacitance per unit area.

Still further, in accordance with the present invention, in the step offorming a gate oxide film of the MISFETs, the capacitor dielectric filmis formed on the capacitor formation trenches. As a result, it ispossible to simplify the manufacturing process. Herein, the MISFETsinclude a MISFET for high voltage and a MISFET for low voltage. It isalso possible to use the gate insulating film of the high-voltage MISFETand the gate insulating film of the low-voltage MISFET differently fordifferent purposes.

Furthermore, in accordance with the present invention, a memory cell isformed, including a first memory gate insulating film, a firstconductive film formed on the first memory gate insulating film, and asecond memory gate insulating film formed on the first conductive film.The second memory gate insulating film and the capacitor dielectric filmdisposed on the capacitor formation trenches are formed by the samestep. As a result, it is possible to simplify the manufacturing process.Further, by using the second memory gate insulating film of the memorycell as the capacitor dielectric film in place of the gate insulatingfilm of the MISFETs, it is possible to improve the reliability of thecapacitor dielectric film and to simplify the manufacturing process.

Representative examples of a semiconductor device in accordance withtypical aspects of the present invention will be briefly described asfollows.

(1) A semiconductor device comprises: semiconductor elements; elementisolation trenches, each for effecting isolation between thesemiconductor elements; capacitor formation trenches; and capacitorelectrodes, each formed inside the capacitor formation trenches via acapacitor dielectric film, characterized in that the capacitor formationtrenches are formed by a step of forming the element isolation trenchesin a semiconductor substrate.

(2) A semiconductor device comprises: semiconductor elements; elementisolation trenches, each for effecting isolation between thesemiconductor elements; a gate insulating film formed on MISFETs of thesemiconductor elements; capacitor formation trenches; a capacitordielectric film formed in the capacitor formation trenches; andcapacitor electrodes formed on the capacitor dielectric film,characterized in that the capacitor dielectric film and the gateinsulating film are formed of a dielectric film of the same layer.

(3) A semiconductor device comprises: semiconductor elements; elementisolation trenches, each for effecting isolation between thesemiconductor elements; a gate insulating film formed on MISFETs of thesemiconductor elements; gate electrodes formed on the gate insulatingfilm; capacitor formation trenches; a capacitor dielectric film formedin the capacitor formation trenches; and capacitor electrodes formed onthe capacitor dielectric film, characterized in that the capacitorelectrodes and the gate electrodes are formed of a dielectric film ofthe same layer.

(4) A semiconductor device comprises: semiconductor elements;

memory cells; element isolation trenches, each for effecting isolationbetween the semiconductor elements; an electric charge storage layerformed in the memory cells; a memory gate insulating film formed on theelectric charge storage layer; capacitor formation trenches; a capacitordielectric film formed in the capacitor formation trenches; andcapacitor electrodes formed on the capacitor formation trenches,characterized in that the capacitor dielectric film and the memory gateinsulating film are formed of a dielectric film of the same layer.

(5) A semiconductor device comprises: semiconductor elements; memorycells; element isolation trenches, each for effecting isolation betweenthe semiconductor elements; an electric charge storage layer formed inthe memory cells; capacitor formation trenches; a capacitor dielectricfilm formed in the capacitor formation trenches; and capacitorelectrodes formed on the capacitor dielectric film, characterized inthat the capacitor electrodes and the electric charge storage layer areformed of a conductive film of the same layer.

(6) A semiconductor device comprises: semiconductor elements; memorycells; element isolation trenches, each for effecting isolation betweenthe semiconductor elements; an electric charge storage layer formed inthe memory cells; a memory gate insulating film formed on the electriccharge storage layer; memory gate electrodes formed on the memory gateinsulating film; capacitor formation trenches; a capacitor dielectricfilm formed in the capacitor formation trenches; and capacitorelectrodes formed on the capacitor dielectric film, characterized inthat the capacitor electrodes and the memory gate electrodes are formedof a conductive film of the same layer.

(7) A semiconductor device comprises: semiconductor elements; elementisolation trenches, each for effecting isolation between thesemiconductor elements; a gate insulating film formed in MISFETs of thesemiconductor elements; gate electrodes formed on the gate insulatingfilm; memory cells; an electric charge storage layer formed in thememory cells; a memory gate insulating film formed on the electriccharge storage layer; memory gate electrodes formed on the memory gateinsulating film; capacitor formation trenches; a capacitor dielectricfilm formed in the capacitor formation trenches; and capacitorelectrodes formed on the capacitor dielectric film, characterized inthat the capacitor electrodes, the gate electrodes, and the memory gateelectrodes are formed of a conductive film of the same layer.

(8) The semiconductor device according to the item (1), wherein thedepth of the capacitor formation trenches is substantially equal to thedepth of the element isolation trenches.

(9) The semiconductor device according to the item (1), wherein thecapacitor formation trenches are formed in the shape of holes, stripes,or a matrix.

(10) The semiconductor device according to the item (2), wherein theMISFETs include a first MISFET for high voltage and a second MISFET forlow voltage, and the thickness of the gate insulating film of the firstMISFET is larger than the thickness of the gate insulating film of thesecond MISFET.

(11) The semiconductor device according to the item (7), wherein thememory gate insulating film and the capacitor dielectric film include amultilayer film composed of a silicon oxide film and a silicon nitridefilm.

(12) The semiconductor device according to the item (7), wherein theelectric charge storage layer includes a silicon nitride film or a Sinano-dot.

(13) The semiconductor device according to the item (7), wherein theelectric charge storage layer is formed of a polysilicon film.

(14) The semiconductor device according to the item (7), wherein thememory gate electrode includes a polysilicon film.

(15) The semiconductor device according to the item (1), wherein thecapacitor dielectric film and each of the capacitor electrodes areformed on a plurality of the capacitor formation trenches.

(16) The semiconductor device according to the item (15), wherein theplurality of the capacitor formation trenches are formed in the shape ofholes, stripes, or a matrix.

(17) A semiconductor device comprises a capacitor having a plurality ofcapacitor formation trenches formed in a capacitor formation region, acapacitor dielectric film, and capacitor electrodes formed on thecapacitor formation region, including the inside of the plurality of thecapacitor formation trenches.

(18) The semiconductor device according to the item (17), wherein theplurality of the capacitor formation trenches are formed in a wellregion; the well region forms one electrode of the capacitor; and thecapacitor electrode forms another electrode of the capacitor.

(19) The semiconductor device according to the item (17), wherein theplurality of the capacitor formation trenches are formed in the shape ofholes, stripes, or a matrix.

(20) The semiconductor device according to the item (7), furthercomprising capacitors, each including the capacitor formation trenches,the capacitor dielectric film, and the capacitor electrodes; and acharge pump circuit formed of a plurality of the capacitors, and aplurality of the MISFETs, wherein the charge pump circuit iselectrically connected to the memory gate electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of basic parts of a semiconductor device,including a memory cell, a MISFET and a capacitor, representingEmbodiment 1 of the present invention;

FIG. 2 is a cross sectional view of the respective parts of one versionof the semiconductor device, as seen along line A-A′, B-B′ and C-C′;respectively, in FIG. 1;

FIG. 3 is a cross sectional view of the respective parts of anotherversion of the semiconductor device, as seen along lines B-B′ and C-C′;respectively, in FIG. 1;

FIG. 4 is a cross sectional view of the respective parts of thesemiconductor device representing Embodiment 1 of the present invention,during a step in the manufacturing process thereof;

FIG. 5 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 4;

FIG. 6 is a plan view of the respective parts of the semiconductordevice as it appears during a manufacturing step, showing an example ofthe capacitor formation trenches;

FIG. 7 is a plan view of the respective parts of the semiconductordevice as it appears during a manufacturing step, showing an example ofthe capacitor formation trenches;

FIG. 8 is a plan view of the respective parts of the semiconductordevice as it appears during a manufacturing step, showing an example ofthe capacitor formation trenches;

FIG. 9 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 5;

FIG. 10 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 9;

FIG. 11 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 10;

FIG. 12 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 11;

FIG. 13 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 12;

FIG. 14 is a plan view of the respective parts of the semiconductordevice as it appears during a manufacturing step, showing a resistpattern used as a mask;

FIG. 15 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 13;

FIG. 16 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 15;

FIG. 17 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing step;

FIG. 18 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 17;

FIG. 19 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 18;

FIG. 20 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 16;

FIG. 21 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 20;

FIG. 22 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 21;

FIG. 23 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 22;

FIG. 24 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 23;

FIG. 25 is a plan view of the respective parts of the semiconductordevice as it appears during a manufacturing step, showing a resistcover;

FIG. 26 is a cross sectional view of the respective parts of asemiconductor device representing an Embodiment 2 of the presentinvention;

FIG. 27 is a cross sectional view of the respective parts of thesemiconductor device representing Embodiment 2 of the present invention,during a step in the manufacturing process thereof;

FIG. 28 is a plan view of the respective parts of the semiconductordevice as it appears during a manufacturing step, showing a resistpattern;

FIG. 29 is a cross sectional view of the respective parts of asemiconductor device representing an Embodiment 3 of the presentinvention;

FIG. 30 is a cross sectional view of the respective parts of thesemiconductor device representing Embodiment 3 of the present invention,during a step in the manufacturing process thereof;

FIG. 31 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 30;

FIG. 32 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 31;

FIG. 33 is a cross sectional view of the MISFET portion of asemiconductor device as it appears during a manufacturing step forEmbodiment 3 of the present invention;

FIG. 34 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 32;

FIG. 35 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 33;

FIG. 36 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 34;

FIG. 37 is a cross sectional view of the respective parts of asemiconductor device representing an Embodiment 4 of the presentinvention;

FIG. 38 is a cross sectional view of the respective parts of thesemiconductor device representing Embodiment 4 of the present invention,showing a step in the manufacturing process thereof;

FIG. 39 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 38;

FIG. 40 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 39;

FIG. 41 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 40;

FIG. 42 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 41;

FIG. 43 is a cross sectional view of the respective parts of asemiconductor device representing an Embodiment 5 of the presentinvention;

FIG. 44 is a cross sectional view of the respective parts of thesemiconductor device representing Embodiment 5 of the present invention,showing a step in the manufacturing process thereof;

FIG. 45 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 44;

FIG. 46 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 45;

FIG. 47 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 46;

FIG. 48 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 47;

FIG. 49 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 48;

FIG. 50 is a cross sectional view of the respective parts of asemiconductor device representing Embodiment 6 of the present invention;

FIG. 51 is a cross sectional view of the respective parts of thesemiconductor device representing Embodiment 6 of the present invention,showing a step in the manufacturing process thereof;

FIG. 52 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 51;

FIG. 53 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 52;

FIG. 54 is a cross sectional view of the respective parts of thesemiconductor device as it appears during a manufacturing stepsubsequent to the step of FIG. 53; and

FIG. 55 is a circuit diagram of a charge pump circuit of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described by way of various embodimentswith reference to the accompanying drawings. Incidentally, throughoutthe drawings, elements having the same function are represented by thesame reference numerals and characters, and a repeated descriptionthereof is omitted.

Embodiment 1

FIG. 1 shows a plan view of the basic parts of a semiconductor devicehaving a nonvolatile memory, which represents one embodiment of thepresent invention. FIG. 1 shows the plan view of a memory cell of thenonvolatile memory on the left-hand side, a MISFET at the central part,and a capacitor (capacitive element) on the right-hand side. FIG. 2shows cross sectional diagrams of the memory cell on the left-hand side,a MISFET for high voltage (a high-voltage MISFET) at the central part,and a capacitor on the right-hand side, which correspond to crosssectional diagrams taken along the lines A-A′, B-B′, and C-C′ of FIG. 1,respectively. The capacitor shown in FIG. 2 uses a gate insulating filmof the high-voltage MISFET as its dielectric film.

FIG. 3 shows the respective cross sectional diagrams of a MISFET for lowvoltage (a low-voltage MISFET) on the left-hand side and a capacitor onthe right-hand side, which are the cross sectional diagrams taken alongB-B′ and C-C′ of FIG. 1, respectively. The capacitor shown in FIG. 3uses a gate insulating film of the low-voltage MISFET as its dielectricfilm.

Thus, the right-hand side of FIG. 2 shows a capacitor formation regionin which a high-voltage gate insulating film of the MISFET is used asthe capacitor dielectric film. Whereas, the right-hand side of FIG. 3shows a capacitor formation region in which a low-voltage gateinsulating film is used as the capacitor dielectric film. Herein, FIG. 3shows only a MISFET and capacitor that are different in configurationfrom those of FIG. 2.

First, the basic configuration in this embodiment 1 will be described byreference to FIGS. 1 to 3.

On a semiconductor substrate 1, a memory cell of a nonvolatile memory, aMISFET, and a capacitor are formed. Incidentally, as the MISFET, anN-channel type MISFET is shown, but a P-channel type MISFET is not shownfor simplification of the following description.

The memory cell is mainly composed of a memory tunnel insulating film(first memory gate insulating film ) 9 formed on a P-type impurity layer(P-type well region) 7 formed on the semiconductor substrate 1, afloating gate electrode 10 which is an electric charge storage layer, acontrol gate electrode (memory gate electrode) 17 a formed on thefloating gate electrode 10, a silicon oxide film 18 formed on thecontrol gate electrode 17 a, a memory gate interlayer film (secondmemory gate insulating film) 11 formed between the floating gateelectrode 10 and the control gate electrode 17 a, a sidewall 26 formedon the sidewall of a memory gate electrode structure 20, an N-typeimpurity layer 23 a serving as a drain region, and an N-type impuritylayer 23 b serving as a source region formed in the P-type impuritylayer (P-type well region). Incidentally, the memory gate electrodestructure 20 is formed of the memory tunnel insulating film 9, thefloating gate electrode 10, the memory gate interlayer film 11, thecontrol gate electrode 17 a, and the silicon oxide film 18.

The memory tunnel insulating film (first memory gate insulating film) 9is composed of, for example, a thermal oxide film. The memory gateinterlayer film (second memory gate insulating film) 11 is composed of,for example, a so-called NONO film in which a silicon nitride film isformed on an oxide film, another oxide film is formed on the siliconnitride film, and another silicon nitride film is formed on the oxidefilm.

The floating gate electrode 10, which is an electric charge storagelayer, is formed of, for example, a polysilicon film. The control gateelectrode (memory gate electrode) 17 a is formed of, for example, amultilayer film of a polysilicon film and a silicide film, such as acobalt silicide (CoSi) film.

The control gate electrode (memory gate electrode) 17 a is electricallyconnected to a word line.

A wiring layer 33 constitutes a bit line, and it is electricallyconnected to the N-type impurity layer 23 a serving as a drain region. Aplug layer 33 a forms a source line, and it is electrically connected tothe N-type impurity layer 23 b serving as a source region. The wiringlayer 33 and the plug layer 33 a are formed of a metal film of, forexample, tungsten (W), or copper (Cu).

In the memory cell, writing of data is performed in the followingmanner. For example, a ground voltage (0 V) is applied to the sourceregion; a voltage of about 5 V is applied to the N-type impurity layer23 a; and a voltage of about 10 V is applied to the control gateelectrode 17 a. Thus, hot electrons are injected and stored in thefloating gate electrode 10, which is an electric charge storage layer.

Data erasure is performed in the following manner. For example, 10 V isapplied to the P-type impurity layer (P-type well region); thesource/drain regions are open; and a high voltage of about −10 V of aninverse potential to that for writing is applied to the control gateelectrode 17 a. Thus, the electrons stored in the floating gateelectrode 10, which is an electric charge storage layer, are drawn tothe P-type impurity layer (P-type well region) 7 by electron tunnelingthrough the memory tunnel insulating film (first memory gate insulatingfilm) 9.

Reading of data is performed in the following manner. For example, 0 Vis applied to the source region; about 1 V is applied to the drainregion; and about 2 to 4 V is applied to the control gate electrode 17a.

Thus, in the writing/erasing operation of the nonvolatile memory cell, ahigh voltage whose absolute value is higher relative to the groundvoltage (0 V) is required. On the other hand, with the desire forreduction in size and power consumption, the trend toward a lowervoltage is accelerating down to use of a ground voltage (0 V) for anexternal power supply voltage Vss to be supplied from an external powersource, and down to about 1.8 to 3.3 V for use as an external powersupply voltage Vcc. Such being the case, a booster circuit, such as acharge pump circuit is mounted on the semiconductor substrate togenerate the respective high voltages from the external power sources.Incidentally, the term high voltage denotes a voltage whose absolutevalue is higher than the external power supply voltage. In thenonvolatile memory in this embodiment, a high voltage of not less thanabout 10 V is required.

For this reason, the MISFETs constituting the peripheral circuitcomprises high-voltage MISFETs having a high-voltage gate insulatingfilm 16 and low-voltage MISFETs having a low-voltage gate insulatingfilm 15 as their respective gate insulating films. The MISFET whose gateelectrode or source/drain is to be applied with a high voltage iscomposed of a high-voltage MISFET.

The capacitor (capacitive element) has a MIS capacitive element formedby utilizing the high-voltage MISFET formation step, and a MIScapacitive element formed by utilizing the low-voltage MISFET formationstep.

The booster circuit, such as a charge pump circuit, is composed of theseMISFETs and capacitors. It is noted that the high-voltage gateinsulating film 16 is formed to have a larger thickness than thethickness of the low-voltage gate insulating film 15.

Element isolation is provided between the semiconductor elements, suchas low-voltage MISFETs, high-voltage MISFETs, and capacitors, by elementisolation trenches 4 and an element isolation insulating film embeddedin the element isolation trenches 4. Namely, the element isolation isachieved by the element isolation trenches 4 in the semiconductorelement formation regions, such as the high-voltage MISFET formationregions, the low-voltage MISFET formation regions, and the capacitorformation regions.

An N-channel type high-voltage MISFET is mainly composed of thehigh-voltage gate insulating film 16 formed as the gate insulating filmof the MISFET on the P-type impurity layer (P-type well region) 7 formedin the semiconductor substrate 1, a gate electrode 17 b of the MISFETformed on the gate insulating film 16 of the high-voltage MISFET, thesidewall 26 formed on the sidewall of a gate electrode structure 21composed of the gate electrode 17 b and a silicon oxide film 18, andN-type impurity layers 24 a and 27 a b serving as source/drain regionsformed in the P-type impurity layer (P-type well region) 7. The N-typeimpurity layers 24 a and 27 a are electrically connected to a wiringlayer 34 a.

The high-voltage gate electrode 17 b is formed of a conductive film ofthe same layer as the control gate electrode (memory gate electrode) 17a of the memory cell.

A capacitor (MIS capacitive element) C formed by utilizing thehigh-voltage MISFET formation step is mainly composed of a dielectricfilm 16 a of the capacitor formed by the step of forming the gateinsulating film of the high-voltage MISFET on capacitor formationtrenches 4 a formed in an N-type impurity layer (N-type well region) 8in the semiconductor substrate 1, and a capacitor electrode 17 c formedby the step of forming the gate electrode 17 b of the high-voltageMISFET. Whereas, an upper electrode structure 22 of the capacitor isformed of the capacitor electrode 17 c and the silicon oxide film 18.

Namely, the capacitor formation trench 4 a is formed by using the losame step as the step of forming the element isolation trench 4 forisolation between the semiconductor elements, such as MISFETs. Thedielectric film 16 a of the capacitor is formed on the side and thebottom of the capacitor formation trench 4 a. The capacitor electrode 17c is formed in such a manner as to fill in the capacitor formationtrench 4 a via the dielectric film 16 a of the capacitor.

Incidentally, the formation of the N-type impurity layer (N-type wellregion) 8 in the capacitor (MIS capacitive element) formation region isaccomplished by the same step as the step of forming the N-type impuritylayer (N-well region) 8 in a p-channel MISFET formation region (notshown).

The capacitor electrode 17 c formed by the same step as the step offorming the gate electrode 17 b of the N-channel type high-voltageMISFET serves as an upper electrode of the capacitor. Whereas, theN-type impurity layer (N-type well region) 8 serves as a lower electrodeof the capacitor. The N-type impurity layer (N-type well region) 8 iselectrically connected to a wiring layer 35 a via an N-type impuritylayer 28 a formed by using the step of forming the source/ drain regionsof the p-channel MISFET. The capacitor electrode 17 c is electricallyconnected to a wiring layer 36 a.

A low-voltage MISFET is mainly composed of the low-voltage gateinsulating film 15 formed as the gate insulating film of the MISFET onthe P-type impurity layer (P-type well region) 7 formed in thesemiconductor substrate 1, a gate electrode 17 b of the MISFET formed onthe low-voltage gate insulating film 15, the sidewall 26 formed on thesidewall of the gate electrode structure 21 composed of the gateelectrode 17 b and the silicon oxide film 18, and N-type impurity layers24 b and 27 b serving as source/drain regions formed in the P-typeimpurity layer (P-type well region) 7. The N-type impurity layers 24 band 27 b are electrically connected to a wiring layer 34 b.

The low-voltage gate electrode 17 b is formed of a conductive film ofthe same layer as the control gate electrode (memory gate electrode) 17a of the memory cell.

A capacitor (MIS capacitive element) formed by utilizing the low-voltageMISFET formation step is mainly composed of a dielectric film 15 a ofthe capacitor formed by the step of forming the gate insulating film ofthe low-voltage MISFET on the capacitor formation trench 4 a formed inthe N-type impurity layer (N-type well region) 8 formed in thesemiconductor substrate 1, and the capacitor electrode 17 c formed bythe step of forming the gate electrode 17 b of the low-voltage MISFET.Whereas, the upper electrode structure 22 of the capacitor is formed ofthe capacitor electrode 17 c and the silicon oxide film 18.

The capacitor formation trench 4 a is formed by using the same step asthe step of forming the element isolation trench 4 for isolation betweenthe semiconductor elements, such as MISFETs. The dielectric film 15 a ofthe capacitor is formed on the side and the bottom of the capacitorformation trench 4 a. The capacitor electrode 17 c is formed in such amanner as to fill in the capacitor formation trench 4 a via thedielectric film 16 a of the capacitor.

The capacitor electrode 17 c formed by the step of forming the gateelectrode 17 b of the low-voltage MISFET constitutes an upper electrodeof the capacitor. Whereas, the N-type impurity layer (N-type wellregion) 8 constitutes a lower electrode of the capacitor. The N-typeimpurity layer (N-type well region) 8 is electrically connected to awiring layer 35 b via an N-type impurity layer 28 b formed by using thestep of forming the source/drain regions of the p-channel MISFET. Thecapacitor electrode 17 c is electrically connected to a wiring layer 36b.

The capacitive elements of the booster circuit, such as a charge pump iscircuit, are composed of these capacitors. The capacitance of thecapacitor, i.e., the area occupied by the MIS capacitive element, mustbe increased for the improvement of the capability of the boostercircuit. This unfavorably results in an increase in the area occupied bythe booster circuit in the chip. Namely, the capacitance value of thecapacitor per unit area is required to be increased. In this embodiment,the capacitor formation trenches 4 a are formed in the surface of thesemiconductor substrate 1 by using the element isolation trenchformation step. Then, the capacitor electrode 17 c of the capacitor (MIScapacitive element) C is formed in such a manner as to be embedded inthe inside thereof. As a result, it is possible to enhance the capacitorcapacitance per unit area, and, hence, it is possible to increase theMIS capacitance as compared with the case where the capacitor (MIScapacitive element) is formed on the flat surface of the semiconductorsubstrate 1, because the area of the capacitor (MIS capacitance), i.e.,the sides and the bottoms of the capacitor formation trenches 4 a,correspond to the MIS capacitance.

Whereas, the capacitor (capacitive element) is formed of a plurality ofcapacitor formation trenches 4 a formed in the capacitor formationregion, the capacitor dielectric film 15 a and the capacitor electrode17 c, that is formed on the capacitor formation region, including theinside of the plurality of the capacitor formation trenches 4 a. As aresult, it is possible to increase the surface area of the capacitor andto improve the capacitor capacitance per unit area.

Further, the capacitor formation trenches 4 a are formed to besubstantially equal in depth to the element isolation trench 4. Thecapacitor formation trenches 4 a are formed by using the step of formingthe element isolation trench 4. Namely, the capacitor formation trenches4 a are formed in the following manner. At least not less than onecapacitor formation trench 4 a is formed by using the step of formingthe element isolation trench 4 for isolation between the respectivesemiconductor elements in the region on the semiconductor substrate 1including the capacitor formation region. The silicon oxide film 5,which is an element isolation insulating film, is then embedded therein.Subsequently, the part of the silicon oxide film 5 which is an elementisolation insulating film of the capacitor formation region is removed.Namely, at least not less than one capacitor formation trench 4 a isformed by the same formation step as with the element isolation trench4.

Whereas, the dielectric films 15 a and 16 a of the capacitors are formedof the insulating films of the same layers as the low-voltage gateinsulating film 15 and the high-voltage gate insulating film 16 of theMISFETs, respectively. The capacitor electrode 17 c is formed of theconductive film of the same layer as that of the gate electrode 17 b ofthe MISFET and the control gate electrode 17 a. Namely, the dielectricfilms 15 a and 16 a of the capacitors are the insulating films formed bythe same formation steps used for formation of the low-voltage gateinsulating film 15 and the high-voltage gate insulating film 16 of theMISFETs, respectively. The capacitor electrode 17 c is the conductivefilm formed by the same formation step used for formation of the gateelectrode 17 b of the MISFET and the control gate electrode 17 a. As aresult, it is possible to simplify the manufacturing process, and it ispossible to improve the capacitor capacitance per unit area.

A description will be given of one example of the charge pump circuit tobe used in this embodiment. As shown in FIG. 55, a charge pump circuit100 boosts the input voltage by the externally received input signals φand/φ and the capacitors C1 to Cn, and it generates a high voltage. Thecapacitors C1 to Cn are formed of the capacitors formed in the capacitorformation region. The transistors T0 to Tn are formed of, for example,the N-type MISFETs out of the foregoing high-voltage MISFETs, each ofwhich is formed in such a manner that the source region 27 a and thegate electrode 17 b are short-circuited. The source region 27 a of sucha transistor T0 is connected to an external voltage Vcc, while the drainregion 27 a is connected to the transistor T1 and the capacitor C1 ofthe subsequent stage.

Herein, when the external voltage Vcc is applied thereto, the electriccharge boosted by the capacitor C1 of the first stage is stored in thecapacitor C2 of the subsequent stage through the transistor T1. Theelectrical charge boosted by the capacitor C2 is stored in the capacitorC3 of the subsequent stage through the transistor T2. Repetition of suchboosting provides an internal voltage Vpp from an output terminal. Suchan internal voltage Vpp is applied to the control gate electrode 17 a ofthe memory cell via a control circuit of the control gate. In thisembodiment, the external voltage Vcc is about 1.8 to 3.3 V, and it ispossible to boost the internal voltage Vpp up to about 18 V.

A method of manufacture of the semiconductor device of this embodiment 1will be described.

First, as shown in FIG. 4, a semiconductor substrate 1 that is made of,for example, P-type single crystal silicon is prepared. Then, thesemiconductor substrate 1 is, for example, thermally oxidized, so that asilicon oxide film 2 with a thickness of about 8 to 10 nm is formed onthe surface.

Then, as the overlying layer of the silicon oxide film 2, a siliconnitride film 3 with a thickness of about 130 to 150 nm is deposited as aprotective layer by, for example, a CVD (Chemical Vapor Deposition)process. Then, as shown in FIG. 5, by using a resist pattern as a mask,the silicon nitride film 3, the silicon oxide film 2, and thesemiconductor substrate 1 are sequentially dry etched, thereby to formelement isolation trenches 4 in the semiconductor substrate 1. At thisstep, at least not less than one capacitor formation trench 4 a also isformed in the capacitor formation region. The capacitor formationtrenches 4 a are formed as stripes, as shown in FIG. 6, in the form ofholes, as shown in FIG. 7, or in a lattice form, as shown in FIG. 8.Namely, a plurality of the capacitor formation trenches 4 a are formedin the shape of holes, stripes, or a lattice.

Thus, by forming the element isolation trenches 4 and the capacitorformation trenches 4 a by the same step, it is possible to simplify themanufacturing process. Further, by forming at least not less than onecapacitor formation trench 4 a on the surface of the capacitor formationregion, it is possible to improve the capacitor capacitance per unitarea. The pattern of the capacitor formation trenches 4 a is not limitedto the shape of holes, stripes, or a matrix, but a pattern in any othershape may also be adopted, so that a change may be made thereto, unlessit departs from the scope of the present invention.

Then, as shown in FIG. 9, on the semiconductor substrate 1, for example,the silicon oxide film 5 is deposited as an insulating film by a CVDprocess. Subsequently, the silicon oxide film 5 is polished by achemical mechanical polishing (CMP) process, so that a part of thesilicon oxide film 5 is left and embedded inside the element isolationtrench 4, thereby to form the element isolation region. The siliconoxide film 5 is also similarly embedded inside each capacitor formationtrench 4 a.

Then, the silicon nitride film 3 is removed by using, for example, a hotphosphoric acid. Subsequently, a P-type impurity, such as boron (B), ision implanted into the memory cell and the N-channel type MISFETformation region by an ion implantation process, thereby to form theP-type impurity layer (P-type well region) 7. Whereas, an N-typeimpurity, such as phosphorus (P) or arsenic (As), is ion implanted intothe capacitors and a P-channel type MISFET formation region (not shown)by an ion implantation process, thereby to form the N-type impuritylayer (N-type well region) 8.

Then, as shown in FIG. 10, for example, the semiconductor substrate 1 isthermally oxidized to form a silicon oxide film with a thickness ofabout 8 to 12 nm on the surface, thereby to form the memory tunnelinsulating film (first memory gate insulating film) 9 of the memorycell. Subsequently, by a CVD process, a polysilicon layer 10 a, which isto be the floating gate electrode (electric charge storage layer) 10 ofthe memory cell, is deposited on the entire surface of the semiconductorsubstrate 1.

Then, as shown in FIG. 11, a multilayer film 11 a of a silicon oxidefilm and a silicon nitride film, serving as the memory gate interlayerfilm (second memory gate insulating film) of the memory cell, is formedon the entire surface of the polysilicon layer 10 a. Further, on themultilayer film 11 a, a silicon nitride film 13 is formed as aprotective layer, thereby to form a memory gate interlayer film 11(below, referred to as a NONO film 11) composed of the multilayer film11 a and the silicon nitride film 13. The NONO film 11 is formed bysequentially stacking a silicon oxide film with a thickness of about 2to 6 nm, a silicon nitride film with a thickness of about 5 to 9 nm, anda silicon oxide film with a thickness of about 3 to 7 nm, and a siliconnitride film with a thickness of about 5 to 15 nm as a protective filmby using, for example, a CVD process.

Then, as shown in FIG. 12, the entire surface of the memory cellformation region is covered with a resist pattern 121. Thereafter, theNONO film 11, the polysilicon layer 10 a, and the memory tunnelinsulating film 9, that are formed on the entire surface of the MISFETformation region and on the entire surface of the capacitor formationregion, are sequentially removed by, for example, dry etching.

Then, as shown in FIG. 13, by using, as a mask, a resist pattern 122,which is formed in the plane pattern shown in FIG. 14, on the entiresurface of the memory cell formation region and on the entire surface ofthe MISFET formation region, the silicon oxide film 5 embedded in thecapacitor formation trenches 4 a of the capacitor is selectively removedby, for example, dry etching.

Then, the gate insulating film of the MISFETs is formed. Herein, thegate insulating film used for the MISFETs and the capacitor dielectricfilm used for the capacitors are formed of a dielectric film of the samelayer. Namely, the gate insulating film used for the MISFETs and thecapacitor dielectric film used for the capacitors are formed by the samestep. In this embodiment, as for the example of the case where thehigh-voltage gate insulating film and the low-voltage insulating filmare formed differently in the same manufacturing process, a descriptionwill be given for (a) the case where the step of forming the capacitordielectric film and the step of forming the high-voltage gate insulatingfilm are the same step; and (b) the case where the step of forming thecapacitor dielectric film and the step of forming the low-voltage gateinsulating film are the same step.

(a) As shown in FIG. 15, for example, the semiconductor substrate 1 isthermally oxidized, thereby to form a silicon oxide film 14 with athickness of about 12 to 16 nm, which is to be the high-voltage gateinsulating film of the MISFETs and the dielectric film of the capacitorson the MISFET formation region and the capacitor formation regionincluding the capacitor formation trenches 4 a.

(b) As shown in FIGS. 16 and 17, a resist pattern 123 is formed on theentire surface of the memory cell formation region and on the entiresurface of the region where the high-voltage gate insulating film isused out of the MISFET formation region and the capacitor formationregion. Namely, the resist pattern 123 is formed in such a manner as toexpose the entire surface of the region where the low-voltage gateinsulating film is used out of the MISFET formation region and thecapacitor formation region.

Then, as shown in FIG. 18, the portion of the silicon oxide film 14,which is formed on the region where the low-voltage gate insulating filmis used in the MISFETs and the capacitors, is removed by, for example,dry etching.

Then, as shown in FIG. 19, after removing the resist pattern 123, forexample, the semiconductor substrate 1 is thermally oxidized. As aresult, a silicon oxide film with a thickness of about 4 to 8 nm, whichis to serve as the is low-voltage insulating film of the MISFETs and thecapacitors, is deposited, thereby to form the low-voltage gateinsulating film 15 and the dielectric film 15 a.

Incidentally, as shown in FIG. 20, due to the thermal oxidation, theportion of the silicon oxide film 14 on the region where thehigh-voltage gate insulating film is used in the MISFETs and thecapacitors is oxidized, resulting in formation of the high-voltage gateinsulating film 16 and the dielectric film 16 a with a thickness ofabout 15 to 20 nm. Namely, on the region where the high-voltage gateinsulating film is used in the MISFET formation region and the capacitorformation region, the high-voltage gate insulating film 16 is formed.

On the other hand, as shown in FIG. 19, in the region where thelow-voltage gate insulating film is used in the MISFET formation regionand the capacitor formation region, the low-voltage gate insulating film15 is formed. The silicon oxide film which is to be the low-voltage gateinsulating film 15 functions as the low-voltage gate insulating film ofthe MISFETs and the capacitor dielectric film of the capacitors.

In this embodiment 1, the subsequent steps will be described mainlybased for the case where the capacitor dielectric film is the same filmas (a) the high-voltage gate insulating film. However, also in the casewhere (b) the low-voltage gate insulating film is described, thesubsequent manufacturing process will be carried out in accordance withthe same procedure. Therefore, a description thereof, except for a part,is omitted.

Then, as shown in FIG. 21, on the NONO film 11 formed on the memorycell, and on the low-voltage gate insulating film 15 and thehigh-voltage gate insulating film 16 formed on the MISFETs and thecapacitors, a polysilicon layer 17, which is to be, for example, thecontrol gate electrode (memory gate electrode) 17 a (see FIG. 2) of thememory cell, is formed. Subsequently, on the polysilicon layer 17, forexample, a silicon oxide film 18 is deposited as an insulating film toserve as a cap layer of the memory cell by a CVD process.

Then, as shown in FIG. 22, a resist pattern 124 is formed on the siliconoxide film 18, so that the silicon oxide film 18, the polysilicon layer17, the NONO film 11, and the polysilicon layer 10 a are dry etched. Asa result, the control gate electrode (memory gate electrode) 17 a andthe floating gate electrode (electric charge storage layer) 10 of thememory cell, the gate electrode 17 b of each of the high-voltage andlow-voltage MISFETs, and the capacitor electrode 17 a of each capacitorare formed. By the steps up to this point, it is possible to form thememory gate electrode structure 20 composed of the memory tunnelinsulating film 9, the floating gate electrode 10, the memory gateinterlayer film 11, the control gate electrode 17 a, and the siliconoxide film 18.

Incidentally, the control gate electrode (memory gate electrode) 17 a ofthe memory cell may also be configured in a polycide structure in whicha silicide film, such as a cobalt silicide (CoSi) film, is formed on thepolysilicon layer.

Then, as shown in FIG. 23, after covering the entire surface of theMISFET formation region and the capacitor formation region with aresist, for example, an N-type impurity, such as arsenic (As), ision-injected into the memory cell formation region in a self-alignedmanner with respect to the memory gate electrode structure 20 by an ionimplantation process. As a result, the N-type impurity layers 23 a and23 b, which are to serve as source/drain regions of the memory cell, areformed. Subsequently, after covering the entire surface of the memorycell formation region and the capacitor formation region with a resist,for example, an N-type impurity, such as phosphorus (P), is ion-injectedinto the MISFET formation region in a self-aligned manner with respectto the gate electrode portion 21 by an ion implantation process. As aresult, the N-type impurity layer 24 a, which is to serve as asource/drain region of the MISFET, is formed.

Whereas, when the gate insulating film of the MISFET is the low-voltagegate insulating film 15, arsenic (As) ions are injected by animplantation process to form the N-type impurity layer 24 b (see FIG.3).

Then, as shown in FIG. 24, on the main surface, i.e., the entire surfaceof the memory cell formation region, the MISFET formation region, andthe capacitor formation region, a silicon nitride film 25 with athickness of about 110 to 150 nm is deposited by, for example, a CVDprocess. Subsequently, after covering the entire surface of the memorycell formation region with a resist, the silicon nitride film 25 on theMISFET formation region and the capacitor formation region isanisotropically dry etched. As a result, the sidewalls 26 are formed onthe sidewalls of the gate electrode of the MISFET and the capacitorelectrode.

Then, an N-type impurity, such as arsenic (As), is ion-injected in aself-aligned manner with respect to the gate electrode portion 21 of theMISFET, the capacitor upper electrode portion 22, and the sidewalls 26.As a result, the N-type impurity layer 27 a, which is to serve as thesource/drain regions of the MISFET, and the N-type impurity region 28 a,which is to serve as a diffusion layer of the lower electrode extractingportion of the capacitor, are formed.

Then, on the main surface, i.e., on the entire surface of the memorycell formation region, the MISFET and capacitor formation regions, forexample, a silicon oxide film (see FIGS. 2 and 3) is deposited as aninterlayer insulating film 29 by a CVD process. Then, the surface isplanarized by a CMP process.

Then, after covering the entire surface of the MISFET formation regionand the capacitor formation region with a resist, the interlayerinsulating film 29 is subjected to patterning. As a result, a connectinghole CONT1 (see FIG. 2) reaching the N-type impurity layers 23 a and 23b of the memory cell formation region is formed in the interlayerinsulating film 29.

Then, as shown in FIG. 25, after covering the entire surface of thememory cell formation region with a resist cover, the interlayerinsulating film 29 is subjected to patterning. As a result, a connectinghole CONT2 (see FIGS. 2 and 3) exposing the N-type impurity layers 24 aand 27 a of the MISFET formation region, a connecting hole CONT3 (seeFIGS. 2 and 3) reaching the N-type impurity layer 28 a of the lowerelectrode extracting portion of the capacitor, and a connecting holeCONT4 (see FIGS. 2 and 3) reaching the capacitor upper electrodestructure 22 are formed.

Then, on the interlayer insulating film 29, including the connectingholes CONT1 to CONT4, for example, a TiN film is deposited by using asputtering process. Subsequently, a W film is deposited on the TiN filmby using a CVD process, so that the connecting holes CONT1 to CONT4 arefilled with the W film. Then, the W film and the TiN film on theinterlayer insulating film 29 are removed by a CMP process, so that theportions of the W film and the TiN film are left in the connecting holesCONT1 to CONT4. Thus, a plug composed of the W film and the TiN film isformed.

Then, on the interlayer insulating film 29 and the plug layer 33 a, aninterlayer insulating film 32 (see FIGS. 2 and 3) composed of a siliconoxide film is deposited by, for example, a CVD process. Subsequently,after forming a lead wire hole 33 b (see FIGS. 2 and 3) to the pluglayer 33 a, for example, a W film is embedded in the lead wire hole 33 bby a sputtering process. The W film is etched back, thereby to form thewiring layer 33 (see FIG. 2) for ensuring an electrical connection tothe N-type impurity layers 23 a and 24 b formed in the capacitor, awiring layer 34 a (see FIG. 2) for ensuring an electrical connection tothe N-type impurity layers 24 a and 27 a formed in the high-voltageMISFET, a wiring layer 34 b (see FIG. 3) for ensuring an electricalconnection to the N-type impurity layers 24 b and 27 b formed in thelow-voltage MISFET, a wiring layer 35 a (see FIG. 2) and a wiring layer35 b (see FIG. 3) for ensuring an electrical connection to the N-typeimpurity layers 28 a and 28 b formed in the capacitors, respectively,and the wiring layer 36 a (see FIG. 2) and the wiring layer 36 b (seeFIG. 3) for ensuring an electrical connection to each capacitor upperelectrode 17 c.

It is possible to form the configuration shown in FIG. 2 based on theforegoing embodiment. Whereas, the diagram for the case where thelow-voltage gate insulating films are used as the gate insulating filmof the MISFET and the capacitor dielectric film of the capacitor is asshown in FIG. 3.

In accordance with such an embodiment 1, it is possible to form theelement isolation trench 4 and the capacitor formation trenches 4 a bythe same step. Further, it is possible to form the high-voltage gateinsulating film 16 or the low-voltage gate insulating film 15 of theMISFET by the same step as the step of forming the dielectric film 16 aor the dielectric film 15 a of the capacitor. Namely, the high-voltagegate insulating film 16 or the low-voltage gate insulating film 15 andthe insulating film used for forming the dielectric film 16 a or thedielectric film 15 a of the capacitor are formed by the same step.Whereas, it is possible to form the gate electrode 17 b of the MISFETand the capacitor electrode 17 c by the same step. Namely, the gateelectrode 17 b of the MISFET and the conductive film used for formingthe capacitor electrode 17 c are formed by the same step. This cansimplify the manufacturing process of the semiconductor device of thisembodiment 1.

Embodiment 2

The configuration of the essential parts of a semiconductor device ofembodiment 2 of the present invention is shown in FIG. 25.

In the foregoing embodiment 1, as shown in FIG. 9, in the step ofremoving the silicon oxide film 5 that is embedded in the capacitorformation trenches 4 a, the mask as shown in FIG. 14 was used as aresist pattern. However, in this embodiment 2, a part of the elementisolation trench 4 may also be used as a part of the capacitor formationregion by performing patterning by using the mask shown in FIGS. 27 and28.

Incidentally, for convenience in the description, a description of thesame part in the following process as was used in the foregoingembodiment 1 will be omitted.

First, after the step shown in FIG. 12 in the foregoing embodiment 1, ais resist pattern 125, as shown in FIGS. 27 and 28, is formed on thesilicon oxide film 5, that is embedded in the element isolation trench 4(see FIG. 12), and in at least not less than one capacitor formationtrench 4 a. Then, dry etching is performed by using the resist pattern125 as a mask, thereby to remove the portions of the silicon oxide film5 embedded in the capacitor formation trench 4 a and a part of theelement isolation trench 4.

Then, the gate insulating film (the low-voltage gate insulating film 15or the high-voltage gate insulating film 16) of the MISFET is formed inthe same manner as with the steps shown in FIG. 15 and subsequentfigures of the foregoing embodiment 1.

The subsequent steps are the same as in the foregoing embodiment 1, andhence a description thereof will be omitted.

Thus, in this embodiment 2, by utilizing a part of the element isolationtrench 4 as a part of the capacitor formation region, without addinganother manufacturing step, it is possible to increase the capacitanceper unit area of the capacitor.

Whereas, this embodiment 2 has been described based on the foregoingembodiment 1, but it can also be carried out in a similar manner basedon the subsequent embodiments.

Embodiment 3

The configuration of the essential parts of a semiconductor device ofembodiment 3 of the present invention is shown in FIG. 29.

In the foregoing embodiment 1, the step of forming the gate insulatingfilms (the low-voltage gate insulating film 15 and the high-voltage gateinsulating film 16) of the MISFETs was the same step as the step offorming the dielectric film 15 a or 16 a of the capacitor. However, inthis embodiment 3, the NONO film 11, which is the memory gate interlayerfilm (second memory gate insulating film) of the memory cell and thecapacitor dielectric film of the capacitor, are formed of the dielectricfilm of the same layer. Namely, the step of forming the NONO film 11,which is the memory gate interlayer film (second memory gate insulatingfilm) of the memory cell, and the step of forming the capacitordielectric film of the capacitor are set to be the same.

Incidentally, for convenience in the description, a description of thesame part in the following process as was used in the foregoingembodiment 1 will be omitted. As for the MISFETs, the gate insulatingfilm is formed so as to be divided into the high-voltage and low-voltagefilms, as with Embodiment 1. However, a description will be mainly givenof the high-voltage one.

After the step of forming the polysilicon layer 10 a, which is to serveas the floating gate electrode (electrode electric charge storage layer)of the memory cell shown in FIG. 10 in the foregoing embodiment 1, theentire surface of the memory cell and MISFET formation regions iscovered with a resist, with the polysilicon layer 10 a being formed.Thereafter, the portion of the polysilicon layer 10 a formed on thecapacitor formation region is removed by dry etching.

Then, as shown in FIG. 30, the entire surface of the memory cellformation region and the MISFET formation region and the region, exceptfor the capacitor formation trenches 4 a, of the capacitor formationregion are covered with a resist pattern 126. Thereafter, the memorytunnel insulating film 9 in the capacitor formation region and theportions of the silicon oxide film 5 embedded in the capacitor formationtrenches 4 a are sequentially removed by dry etching.

Then, as shown in FIG. 31, on the entire surface of the memory cellformation region, and the entire surface of the MISFET formation region,and the capacitor formation region, the NONO film 11, which is to serveas the gate interlayer film of the memory cell, is formed by the samestep as in Embodiment 1. Namely, the insulating film that is used forthe formation of the memory gate interlayer film 11 and the dielectricfilm of the capacitor are formed by the same step.

Then, as shown in FIG. 32, the entire surface of the memory cell andcapacitor formation region is covered with a resist 127. Thereafter, theNONO film 11, the polysilicon layer 10 a, and the memory tunnelinsulating film 9 formed on the MISFET formation region are removed bydry etching. Whereas, as shown in FIG. 33, they are also removedsimilarly in the region for forming the low-voltage gate insulating film15.

Subsequently, the high-voltage gate insulating film 16 and thelow-voltage insulating film 15 are formed in the MISFET formationregions. As for the processes for forming the high-voltage gateinsulating film 16 and the low-voltage insulating film 15, differentprocesses are respectively adopted for (a) the high-voltage gateinsulating film and (b) the low-voltage gate insulating film, as withthe foregoing embodiment 1. The manufacturing processes thereof arerespectively the same as in Embodiment 1, and hence a descriptionthereof will be omitted (see FIGS. 34 and 35).

Then, as shown in FIG. 36, on the NONO film 11 that is formed on thememory cell and capacitor formation regions and the gate insulating filmthat is formed on the MISFET formation region, the polysilicon film,which is to serve as the control gate electrode (memory gate electrode)17 a of the memory cell, and the silicon oxide film 18, which is toserve as a cap layer, are sequentially deposited by a CVD process.

Then, a resist pattern 128 is formed. The memory gate electrodestructure 20, the gate electrode structure 21 of the MISFET, and thecapacitor upper electrode structure 22 are formed by dry etching usingthe resist pattern 128. Namely, the conductive film that is used for theformation of the memory gate electrode structure 20, the gate electrodestructure 21 of the MISFET, and the capacitor upper electrode structure22 is formed by the same step.

Below, it is possible to form the semiconductor device having thenonvolatile memory shown in FIG. 29 through the same manufacturingprocess as was used in the foregoing embodiment 1, and hence adescription thereof will be omitted.

Thus, by forming the capacitor dielectric film of the capacitor and thememory gate interlayer film of the memory cell by the same step, it ispossible to simplify the manufacturing process. Further, by using theNONO film 11 in place of the low-voltage gate insulating film 15 or thehigh-voltage gate insulating film 16 of the MISFET as the capacitordielectric film of the capacitor, it is possible to implement a highreliability capacitor dielectric film.

Embodiment 4

The configuration of the main parts of a semiconductor device ofembodiment 4 of the present invention is shown in FIG. 37.

In the foregoing embodiment 1, as shown in the steps of forming thememory cell of FIGS. 10 to 22, the polysilicon layer 10 a is formed asthe electric charge storage layer of the memory cell. However, a siliconnitride film 41 is used to form the electric charge storage layer.Incidentally, the silicon nitride film 41 stores electric charges bycapturing electrons in the trap of the silicon nitride film 41.

For convenience in description, a description of the same part in thefollowing process as was used in the foregoing embodiment 1 will beomitted.

After the step shown in FIG. 10 in the foregoing embodiment 1, as shownin FIG. 38, on the memory tunnel insulating film 9, the silicon nitridefilm 41 and a silicon oxide film 42 are sequentially deposited by using,for example, a CVD process. The silicon nitride film 41 has a functionof storing electric charges as a substitute for the floating gateelectrode of the memory cell.

Then, as shown in FIG. 39, the entire surface of the memory cellformation region is covered with a resist pattern 129. Then, theportions of the silicon oxide film 42, the silicon nitride film 41 andthe memory tunnel insulating film 9 that are formed on the MISFETformation region and the capacitor formation region are sequentiallyremoved by etching. Subsequently, the resist pattern 122 shown in FIG.14 in the foregoing embodiment 1 is formed, and the portions of thesilicon oxide film 5 embedded in the capacitor formation trenches 4 aare removed.

Subsequently, as shown in FIG. 40, the gate insulating films (thelow-voltage gate insulating film 15 and the high-voltage gate insulatingfilm 16) of the MISFETs and the dielectric film 16 a are formed on theMISFET formation regions and the capacitor formation region,respectively, by the same step as in the foregoing embodiment 1.

Then, as shown in FIG. 41, on the silicon oxide film 42 formed on thememory cell formation region, and on the low-voltage gate insulatingfilm 15 or the high-voltage gate insulating film 16 formed on the MISFETformation region and the capacitor formation region, a polysilicon film44 and a silicon oxide film 45 are sequentially deposited by using a CVDprocess.

Then, as shown in FIG. 42, patterning is performed by using a resistpattern 130 as a mask, thereby to form a memory gate electrode 44 a, agate electrode 44 b of the MISFET, and an upper electrode 44 c of thecapacitor. Namely, the memory gate electrode 44 a, the gate electrode 44b of the MISFET, and the upper electrode 44 c of the capacitor arecomposed of a conductive film of the same layer, and the conductive filmused for the formation of the memory gate electrode 44 a, the gateelectrode 44 b of the MISFET, and the upper electrode 44 c of thecapacitor is formed by the same step. In accordance with the steps up tothis point, it is possible to form a memory gate electrode structure 40that is composed of the memory tunnel insulating film 9, the siliconnitride film 41, the silicon oxide film 42, the memory gate electrode 44a, and the silicon oxide film 45.

In the subsequent steps, the semiconductor device having the nonvolatilememory shown in FIG. 37 is formed through the same steps as used in theforegoing embodiment 1, and hence a description thereof will be omitted.

Thus, in this embodiment 4, the electric charge storage layer of thememory cell is formed by using the silicon nitride film 41 in place ofthe polysilicon layer 10 a in the foregoing embodiment 1. However, ascompared with the case where the polysilicon film 10 a, which is acontinuous conductive film, performs electric charge storage, theelectron traps in the silicon nitride film 41 are discontinuous anddiscrete. Therefore, even when a charge leakage path, such as a pinhole,occurs in a part of the memory tunnel insulating film 9, all of thestored electric charges will not disappear. As a result, it is possibleto establish inherently strong retention characteristics.

Whereas, the electric charge storage layer of the memory cell may alsobe formed of so-called Si nano-dots composed of silicon spheres eachhaving a diameter of several nanometers in place of the silicon nitridefilm 41. Also, in such a case, it is possible to obtain the foregoingsame effects as obtained in this embodiment 4.

Embodiment 5

The configuration of the main parts of a semiconductor device ofembodiment 5 of the present invention is shown in FIG. 43.

In the foregoing embodiment 4, as a modified example of the foregoingembodiment 1, the memory gate electrode structure 40 was formed in placeof the memory gate electrode structure 20. However, in this embodiment5, the gate electrode structure is formed in a so-called split-gate typeas a memory gate electrode structure 50, as shown in FIG. 43.

Incidentally, for convenience in the description, a description of thesame part in the following process as was used in the foregoingembodiment 1 will be omitted.

After the step shown in FIG. 10 in the foregoing embodiment 1, as shownin FIG. 44, on the memory tunnel insulating film 9, a polysilicon film51 and a silicon oxide film 52 are sequentially deposited by, forexample, a CVD process. Incidentally, the silicon oxide film 52 may alsobe formed by thermally oxidizing the surface of the polysilicon film 51.

Then, as shown in FIG. 45, a resist pattern 131 is formed on the siliconoxide film 52 of the memory cell formation region. Thereafter, thesilicon oxide film 52, the polysilicon film 51, and the memory tunnelinsulating film 9 are sequentially patterned, and selectively removed.The electric charge storage layer of the memory cell is formed of thepolysilicon film 51.

Then, as shown in FIG. 46, a resist pattern 132 is formed by using thesame mask as the mask shown in FIG. 14 in the foregoing embodiment 1.Thus, the silicon oxide film 5 formed in the capacitor formationtrenches 4 a of the capacitor is selectively removed.

Then, as shown in FIG. 47, a silicon oxide film, which is to serve as agate insulating film 53 of the MISFET, is formed by using, for example,a CVD process. Whereas, the silicon oxide film to be the gate insulatingfilm 53 of the MISFET may also be formed into different films by thesame steps as the steps of forming the high-voltage gate insulating film16 (see FIG. 2) and the low-voltage gate insulating film 15 (see FIG. 3)in the foregoing embodiment 1.

Then, as shown in FIG. 48, on the gate insulating film 53, a polysiliconfilm 54 and a silicon oxide film 55 are sequentially deposited by using,for example, a CVD process.

Then, as shown in FIG. 49, a resist pattern 133 is formed. Thus, thesilicon oxide film 55 and the polysilicon film 54 are selectivelyremoved by patterning. As a result, it is possible to form a memory gateelectrode 54 a, a gate electrode 54 b of the MISFET, and an upperelectrode 54 c of the capacitor. In accordance with the steps up to thispoint, it is possible to form is a memory gate electrode structure 50that is composed of the memory tunnel insulating film 9, the polysiliconfilm 51, the silicon oxide film 52, the gate insulating film 53, thememory gate electrode 54 a, and the silicon oxide film 55.

In the subsequent steps, it is possible to form the semiconductor devicehaving the nonvolatile memory shown in FIG. 43 through the samemanufacturing steps as used in the foregoing embodiment 1, and hence adescription thereof will be omitted.

Thus, also when the memory gate electrode portion is formed in theconfiguration as shown in this embodiment 5, it is possible to obtainthe same effects as obtained in the foregoing embodiment 1.

Embodiment 6

The configuration of the main parts of a semiconductor device ofembodiment 6 of the present invention is shown in FIG. 50.

In the foregoing embodiment 1, the gate electrode of the MISFET and theupper electrode of the capacitor were formed of the polysilicon layer 17(see FIG. 21) serving as the control gate electrode 17 a (see FIG. 2) ofthe memory cell. However, in this embodiment 6, these electrodes areformed by using the polysilicon layer 10 a serving as the floating gateelectrode 10 (see FIG. 2) of the memory cell and the polysilicon layer17 serving as the control gate electrode 17 a.

Incidentally, for convenience in the description, a description of thesame part in the following process as was used in the foregoingembodiment 1 will be omitted.

After the step shown in FIG. 9 in the foregoing embodiment 1, as shownin FIG. 51, the region except for the capacitor formation trenches 4 ais covered with a resist pattern 134. Thus, the silicon oxide film 5embedded in the capacitor formation trenches 4 a is etched and removed.

Then, as shown in FIG. 52, for example, the semiconductor substrate 1 isthermally oxidized, thereby to form a gate insulating film 60 on theMISFET formation region, and, simultaneously, to also form the gateinsulating film 60 on the capacitor formation trenches 4 a. Herein, thegate insulating film 60 may also be formed into different films by thesame steps as the steps of forming the high-voltage gate insulating film16 (see FIG. 2) and the low-voltage gate insulating film 15 (see FIG. 3)in the foregoing embodiment 1. Further, at this step, the same oxidefilm as the gate insulating film 60 is also formed on the memory cellformation region.

Then, the entire surface of the MISFET formation region and thecapacitor formation region is covered with a resist. Thereafter, theportion of the oxide film on the surface of the memory cell formationregion is etched and removed. Subsequently, the semiconductor substrate1 is thermally oxidized, thereby to form a silicon oxide film 61, whichis to serve as the memory tunnel insulating film on the memory cellformation region.

Then, as shown in FIG. 53, on the entire surface of the semiconductorsubstrate 1, a polysilicon film 63, which is to serve as a floating gateelectrode (electric charge storage layer) of the memory cell, isdeposited by using a CVD process. Then, a NONO film 64, which is toserve as a memory gate interlayer film, is formed on the polysiliconfilm 63.

Then, as shown in FIG. 54, a part of the NONO film 64 that is formed onthe MISFET formation region and the capacitor formation region isselectively removed. Thereafter, on the exposed polysilicon film 63 andNONO film 64, a polysilicon film 65, which is to serve as a control gateelectrode (memory gate electrode) of the memory cell, and a siliconoxide film 66, which is to serve as a cap layer, are sequentiallydeposited by using a CVD process. This allows the establishment ofcontinuity between the polysilicon film 63 and the polysilicon film 65that are formed on the MISFET formation region and the capacitorformation region. Subsequently, by dry etching using a resist pattern,the silicon oxide film 66, the polysilicon film 65, the NONO film 64,the polysilicon film 63, and the silicon oxide film 61 are patternedand, thereby, selectively removed. As a result, it is possible to formmemory gate electrodes 63 a and 65 a, gate electrodes 63 b and 65 b ofthe MISFET, and capacitor upper electrode 63 c and 65 c, as shown inFIG. 50.

In the subsequent steps, it is possible to form the semiconductor devicehaving the nonvolatile memory of this embodiment 6, as shown in FIG. 50,through the same steps as used in the foregoing embodiment 1, and,hence, a description thereof will be omitted.

As described above, the floating gate electrode and the memory gateelectrode of the memory cell are formed by the same step for the gateelectrode of the MISFET and the capacitor upper electrode. Namely, thefloating gate electrode and the memory gate electrode of the memorycell, the gate electrode of the MISFET, and the capacitor upperelectrode are composed of a conductive film of the same layer. Theconductive film used for the formation of the floating gate electrodeand the memory gate electrode of the memory cell, the gate electrode ofthe MISFET, and the capacitor upper electrode is formed by the samestep. By performing the formation thereof in this manner, it is possibleto simplify the manufacturing process.

Thus, instead of forming the gate electrode of the MISFET and thecapacitor upper electrode only from the polysilicon film which is toserve as the control gate electrode of the memory cell, when both thepolysilicon film, which is to serve as the floating gate electrode ofthe memory cell, and the polysilicon film, which is to serve as thecontrol gate electrode, are used, it is possible to obtain the sameeffects as obtained in the foregoing embodiments 1 to 5.

Up to this point, the present invention has been described specificallyby way of various embodiments of the invention, which should not beconstrued as limiting the scope of the present invention. It is needlessto say that various changes and modifications may be made withoutdeparting the scope of the invention. For example, each of the foregoingembodiments 1 to 6 may also be combined with one or a plurality of theother embodiments.

The effects obtainable in accordance with typical aspects of the presentinvention as disclosed in this application will be briefly described asfollows.

A capacitor (capacitive element) is formed of a plurality of capacitorformation trenches that are formed in a capacitor formation region, acapacitor dielectric film formed on the capacitor formation region,including the inside of the plurality of the capacitor formationtrenches, and capacitor electrodes.

As a result, it is possible to increase the surface area of thecapacitor, and thereby to improve the capacitor capacitance per unitarea.

On a semiconductor substrate, an element isolation trench and thecapacitor formation trenches formed in the capacitor are formed by thesame step. As a result, it is possible to simplify the manufacturingprocess of the semiconductor device.

Whereas, the gate insulating film of the MISFET and the dielectric filmof the capacitor on the capacitor formation trenches are formed by thesame step. As a result, it is possible to simplify the manufacturingprocess of the semiconductor device.

Further, the capacitor dielectric film in the capacitor formationregion, and a memory gate interlayer film of a memory cell are formed bythe same step. As a result, it is possible to simplify the manufacturingprocess of the semiconductor device.

Still further, the dielectric film of the capacitor is formed by usingthe memory gate interlayer film (NONO film) of the memory cell in placeof using a gate insulating film of a MISFET. As a result, it is possibleto form a high reliability capacitor dielectric film.

1. A semiconductor device comprising: semiconductor elements formed in afirst well; element isolation trenches each for isolation between thesemiconductor elements; capacitor formation trenches formed in a secondwell, and the depth of the capacitor formation trenches is equal to thedepth of the element isolation trenches; and capacitor electrodes eachformed inside the capacitor formation trenches via a capacitordielectric film.
 2. A semiconductor device according to claim 1, whereinthe capacitor formation trenches are formed in the shape of holes,stripes, or a matrix.
 3. A semiconductor device according to claim 1,wherein an insulating film is buried in the element isolation trenches.4. A semiconductor device comprising: semiconductor elements each havinga gate insulating film; element isolation trenches for isolation betweenthe semiconductor elements; capacitor formation trenches; and acapacitor dielectric film formed in the capacitor formation trenches,wherein the semiconductor elements are formed in a first well, whereinthe capacitor formation trenches are formed in a second well, whereinthe depth of the capacitor formation trenches is equal to the depth ofthe element isolation trenches, and wherein the capacitor dielectricfilm and the gate insulating film are formed of a same layer.
 5. Asemiconductor device according to claim 4, wherein the capacitorformation trenches are formed in the shape of holes, stripes, or amatrix.
 6. A semiconductor device according to claim 4, wherein thesemiconductor elements include a first MISFET for high voltage and asecond MISFET for low voltage, wherein the thickness of the gateinsulating film of the first MISFET is larger than the thickness of thegate insulating film of the second MISFET, and wherein the capacitordielectric film is formed of a same layer as that of the gate insulatingfilm of the first MISFET.
 7. A semiconductor device according to claim4, wherein the capacitor dielectric film and the gate insulating filminclude a silicon oxide film.
 8. A semiconductor device according toclaim 4, wherein an insulating film in buried in the element isolationtrenches.
 9. A semiconductor device comprising: semiconductor elementseach having a gate electrode; element isolation trenches each forisolation between the semiconductor elements; capacitor formationtrenches; and capacitor electrodes formed in the capacitor formationtrenches, wherein the semiconductor elements are formed in a first well,wherein the capacitor formation trenches are formed in a second well,wherein the depth of the capacitor formation trenches is equal to thedepth of the element isolation trenches, and wherein the capacitorelectrodes and the gate electrodes are formed of a same layer.
 10. Asemiconductor device according to claim 9, wherein the capacitorformation trenches are formed in the shape of holes, stripes, or amatrix.
 11. A semiconductor device according to claim 9, wherein thesemiconductor elements include a first MISFET for high voltage and asecond MISFET for low voltage, and wherein the capacitor electrodes areformed of a same layer as that of the gate electrode of the firstMISFET.
 12. A semiconductor device according to claim 9, wherein thecapacitor electrodes and the gate electrodes include a poly-siliconfilm.
 13. A semiconductor device according to the claim 9, wherein aninsulating film is buried in the element isolation trenches.
 14. Asemiconductor device comprising: semiconductor elements formed in afirst well; memory cells formed in a third well; capacitor elementsformed in a second well; and element isolation trenches each forisolation between the semiconductor elements, wherein each semiconductorelement has a first insulating film and a first conductive film formedover the first insulating film, wherein each memory cell has an electriccharge storage layer, a second insulating film formed over the electriccharge storage layer and a second conductive film formed over the secondinsulating film, wherein each capacitor element has capacitor formationtrenches, the first insulating film formed in the capacitor formationtrenches and the first conductive film formed over the first insulatingfilm, and wherein the depth of the capacitor formation trenches is equalto the depth of the element isolation trenches.
 15. A semiconductordevice according to claim 14, wherein the capacitor formation trenchesare formed in the shape of holes, stripes, or a matrix.
 16. Asemiconductor device according to claim 14, wherein the semiconductorelements include a first MISFET for high voltage and a second MISFET forlow voltage, the first MISFET including the first insulating film, andwherein the first insulating film of the capacitor element is formed ofthe same film as the first insulating film of the first MISFET.
 17. Asemiconductor device according to claim 14, wherein the semiconductorelements and the capacitor elements constitute a charge pump circuit,and wherein the charge pump circuit is electrically connected to thesecond conductive film of the memory cell.
 18. A semiconductor deviceaccording to claim 14, wherein an insulating film is buried in theelement isolation trenches.
 19. A semiconductor device comprising:memory cells formed in a third well; capacitor elements formed in asecond well; and element isolation trenches each for isolation betweenthe memory cells, wherein each memory cell has an electric chargestorage layer, a second insulating film formed over the electric chargestorage layer and a second conductive film formed over the secondinsulating film, wherein each capacitor element has capacitor formationtrenches and the second insulating film formed in the capacitorformation trenches, and wherein the depth of the capacitor formationtrenches is equal to the depth of the element isolation trenches.
 20. Asemiconductor device according to claim 19, wherein the capacitorformation trenches are formed in the shape of holes, stripes, or amatrix.
 21. A semiconductor device according to claim 19, wherein eachcapacitor element further has the second conductive film formed over thesecond insulating film in the capacitor formation trench.
 22. Asemiconductor device according to claim 19, wherein the electric chargestorage layer includes a silicon nitride film or a Si nano-dot.
 23. Asemiconductor device according to claim 19, wherein the electric chargestorage layer is formed of a poly-silicon film.
 24. The semiconductordevice according to claim 19, wherein the second insulating filmincludes a silicon oxide film and a silicon nitride film.
 25. Asemiconductor device according to claim 19, wherein an insulating filmis buried in the element isolation trenches.
 26. A semiconductor devicecomprising: memory cells formed in a third well; capacitor elementsformed in a second well; and element isolation trenches each forisolation between the memory cells, wherein each memory cell has anelectric charge storage layer and a second conductive film formed overthe electric charge storage layer, wherein each capacitor element hascapacitor formation trenches, and the electric charge storage layerformed in the capacitor formation trenches, and wherein the depth of thecapacitor formation trenches is equal to the depth of the elementisolation trenches.
 27. A semiconductor device according to claim 26,wherein the capacitor formation trenches are formed in the shape ofholes, stripes, or a matrix.
 28. A semiconductor device according toclaim 26, wherein each capacitor element further has the secondconductive film formed over the second insulating film in the capacitorformation trench.
 29. A semiconductor device according to claim 26,wherein the charge storage layer includes a silicon nitride film.
 30. Asemiconductor device according to claim 26, wherein an insulating filmis buried in the element isolation trenches.